The present invention relates to a semiconductor integrated circuit, and in particular, to a semiconductor integrated circuit mounting a logic circuit including a storage element.
In order to detect the stuck-at fault and the like with respect to the logic circuit, the method of scanning a logic circuit is widely used. This method provides the advantage in which the fault can be efficiently detected. Because, when this method is used, it becomes possible to directly manipulate the value of the flipflop (hereinafter, referred to as xe2x80x9cFFxe2x80x9d) within the logic circuit.
The process of detecting (hereinafter, referred to as xe2x80x9ctestingxe2x80x9d) the fault with respect to the scanned logic circuit will be explained with reference to the drawings. FIG. 22 is the circuit configuration diagram showing the scan FF used in the conventional technique. This is an example of the multiplexer-type scan FF (hereinafter, referred to as xe2x80x9cMUX-type scan FFxe2x80x9d). In this configuration, a multiplexer (hereinafter, referred to as xe2x80x9cMUXxe2x80x9d) g2602 is connected to an input terminal D of a FF g2601. A signal (hereinafter, referred to as xe2x80x9cinput signal from logic circuitxe2x80x9d or xe2x80x9clogic input signalxe2x80x9d) for performing a normal operation at a front stage is applied through a logic input signal line to the MUX g2602 from a group of logic gates (hereinafter, referred to as xe2x80x9cuser logic circuitxe2x80x9d). Furthermore, a signal for the scan (hereinafter, referred to as xe2x80x9cscan-in signalxe2x80x9d) from a FF at the front stage is input through a scan-in signal line. Furthermore, a signal (hereinafter, referred to as xe2x80x9cscan-enable signalxe2x80x9d) for controlling to change over which the FF g2601 fetches the logic input signal or the scan-in signal is input through a scan-enable signal line. A logic output signal line for propagating a signal (hereinafter, referred to as xe2x80x9coutput signal to logic circuitxe2x80x9d or xe2x80x9clogic output signalxe2x80x9d) which is input to a user logic circuit at the rear stage, and a scan-out signal line for propagating a signal for scan (hereinafter, referred to as xe2x80x9cscan-out signalxe2x80x9d) which is input to a FF at the rear stage are branched in the fork-shape and are connected to an output terminal Q of the FF g2601.
FIG. 23 is a diagram showing a logic circuit scanned by the conventional technique. This is an example of the scanned logic circuit formed by connecting the MUX-type scan FFs in multi-stages. In this configuration, the scan-out signal lines of the MUX-type scan FFs g2701 and g2702 are respectively connected to the scan-in signal lines of the MUX-type scan FFs g2702 and g2703 to form the signal paths of logic circuit (hereinafter, referred to as xe2x80x9cpathsxe2x80x9d). Hereinafter, these paths are referred to as xe2x80x9cscan pathsxe2x80x9d. Also, the scan-in signal line of the MUX-type scan FF g2701 is connected to the terminal (scan-in terminal) which receives the scan-in signal from the outside of the semiconductor integrated circuit chip (hereinafter, referred to as xe2x80x9cchipxe2x80x9d). The scan-out signal line of the MUX-type scan FF g2703 is connected to the terminal (scan-out terminal) which outputs the scan-out signal to the outside of the chip.
The test using the scan FF is conducted by sequentially repeating the following operations.
(1) An operation for substituting the initial values for test into the respective FFs within the logic circuit (hereinafter, referred to as xe2x80x9cscan-in operationxe2x80x9d);
(2) An operation for inputting the initial values into the user logic circuits from the respective FFs to fetch into the respective FFs the test result values which are output from the user logic circuits (hereinafter, referred to as xe2x80x9clogic test operationxe2x80x9d); and
(3) An operation for collecting the test result values from the respective FFs (hereinafter, referred to as xe2x80x9cscan-out operationxe2x80x9d).
The reference numerals a2704, a2705 and a2706 denote the signal flow at scan-in operation, the signal flow at logic test operation and the signal flow at scan-out operation, respectively.
FIG. 24 is a timing chart showing the operation of the scan FF g2603 used in the conventional technique. First, at scan-in operation, the scan-enable signal is set to xe2x80x9cHighxe2x80x9d so that the respective FFs can fetch the scan-in signal. In order to substitute the initial values for test into the respective FFs, the clock signal is made to transit (s2801) a plurality of times to carry out the shift operation through the scan path. Next, at logic test operation, the scan-enable signal is set to xe2x80x9cLowxe2x80x9d (s2802) so that the respective FFs can fetch the logic output signals. In order to input the initial values for test into the user logic circuits, the clock signal is made to transit one time, and in order to fetch the test result values into the respective FFs, the clock signal is made to transit one time (s2803). Moreover, at scan-out operation, in order that the respective FFs can output the scan-out signals, the scan-enable signal is set again to xe2x80x9cHighxe2x80x9d (s2804). In order to collect the test result values from the respective FFs, the shift operation similar to the scan-in operation is performed.
However, at scan-in and scan-out operations (hereinafter, referred to as xe2x80x9cscan-mode operationxe2x80x9d altogether), there is a trend that the probability of operating a logic circuit is usually increased as compared with at user-mode operation. For this reason, the fault detection mistakes due to the excessive voltage drops and the fear of the chip destruction due to the heat generation have been pointed out as the devices become finer, as described in IEEE Computer, vol.32, no.11, p.61, 1999, for example.
In order to avoid this problem, heretofore, it is considered to suppress the power consumption by reducing the frequency at scan-mode operation, as described in DESIGN FOR AT-SPEED TEST, DIAGNOSIS AND MEASUREMENT, Kluwer Academic Publishers, p. 24, 1999, for example. According to this conventional technique, as shown in FIG. 24, the frequency of the system clock signal at logic test operation (s2803) is made to be the frequency at normal operation of the user logic circuit. Whereas, the frequency of the system clock signal at scan-mode operation (s2801) is lowered to reduce the power consumption due to the operation of the user logic circuit at scan-in operation. However, in this method, the time required for the test (test time) becomes long, so that the advantage due to scan will be deteriorated. This is because that the time required for the scan-mode operation normally occupies the most part of the whole test time. As a result, the cost required for the test (hereinafter, referred to as xe2x80x9ctest costxe2x80x9d) will be increased.
Furthermore, it is considered to reduce the power consumption at scan-mode operation by adding a FF, which is dedicated for the scan-mode operation, within the chip, as described in Digest of Papers 1978 Semiconductor Test Conference, pp. 152-158, for example. However, in this method, the area of the chip will be increased to a great extent. In this respect, according to our inventors"" study, it is found that the chip area increases by about 50% as compared with the normal condition.
As mentioned above, in the conventional technique, there is a problem in that when it is intended to detect the fault with respect to the scanned logic circuit, the time required for the test becomes long, or the area of the chip increases to a great extent.
An object of the present invention is to provide a semiconductor integrated circuit capable of decreasing the test cost as compared with the conventional technique by reducing the test time and by suppressing the increase of the chip area.
Another object of the present invention is to provide a manufacturing method of a semiconductor integrated circuit which decreases the test cost by reducing the test time.
There is constituted a scan flipflop (scan latch) as a storage circuit, wherein the storage circuit comprises:
a first logic gate for receiving a first signal and a second signal, and for selectively outputting either the first signal or the second signal in accordance with a control signal;
a first storage element for receiving a clock signal, for storing an output signal of the first logic gate in response to the clock signal, and for outputting the stored signal in response to the clock signal; and
a second logic gate for receiving an output signal of the first storage element, and for outputting or fixing the output signal of the first storage element in response to the control signal.
There is constituted a semiconductor integrated circuit having a scan path, wherein the semiconductor integrated circuit comprises:
a first storage circuit including first and second input terminals, first and second output terminals, and a first control terminal for receiving a control signal;
a logic circuit for receiving an output signal of the first output terminal of the first storage circuit, for performing a predetermined processing on the output signal, and for outputting a result of the processing; and
a second storage circuit including third and fourth input terminals, and a second control terminal for receiving the control signal, wherein
when the control signal is in a first state, the first storage circuit stores a first signal, which is input to the first input terminal, to output the stored first signal to the first output terminal;
when the control signal is in a second state, the first storage circuit makes a voltage of the first output terminal to be any voltage of the operation voltages of the logic circuit, and stores a second signal, which is input to the second input terminal, to output the stored second signal to the second output terminal;
when the control signal is in the first state, the second storage circuit stores an output of the logic circuit which is input to the third input terminal; and
when the control signal is in the second state, the second storage circuit stores an output of the second output terminal of the first storage circuit which is input to the fourth input terminal.
Furthermore, in the present invention, a scan FF able to fix the output-to-logic signal, a scan FF able to fix the scan-out signal, a scan FF selectable of the output-to-logic signal and scan-out signal, and a normal scan FF are used properly depending on the characteristics (power consumption and delay time) of the logic circuit.
Such a scan FF is registered as one cell in a cell library which describes its function, power consumption and delay information, and is used in the design of a semiconductor integrated circuit.
Furthermore, the design of a semiconductor integrated circuit which uses a plurality of scan FFs properly is achieved as follows. That is, (1) the semiconductor integrated circuit is designed by using the scan FF able to fix the output-to-logic signal, and (2) a scan FF forming a start point of a path which does not satisfy the timing specifications is replaced with the normal scan FF. Also, after the layout, the replacement with the scan FF having a scan-out fixing function is carried out based on the power consumption.
Moreover, a semiconductor integrated circuit apparatus is manufactured as follows. That is, the mask pattern of physical layout of the semiconductor integrated circuit designed as mentioned above is reflected to a semiconductor wafer to form the semiconductor integrated circuit apparatus on the semiconductor wafer. Then, a logic test is conducted on the formed semiconductor integrated circuit apparatus. Here, in the logic test, the frequency at the scan is made equal to the frequency at the logic test. In particular, the clock frequency at the scan is made equal to the clock frequency used at normal operation, so that the rate of the test cost occupying in the manufacturing cost is made small.